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tps54821 slvsb14a ? october 2011 ? revised november 2014 tps54821 4.5 v to 17 v input, 8 a synchronous step down swift ? converter with hiccup 1 features 3 description the tps54821 in thermally enhanced 3.5 mm x 3.5 1 ? integrated 26 m ? / 19 m ? mosfets mm qfn package is a full featured 17 v, 8 a ? split power rail: 1.6 v to 17 v on pvin synchronous step down converter which is optimized ? 200 khz to 1.6 mhz switching frequency for small designs through high efficiency and integrating the high-side and low-side mosfets. ? synchronizes to external clock further space savings are achieved through current ? 0.6v 1% voltage reference over temperature mode control, which reduces component count, and ? low 2 a shutdown quiescent current by selecting a high switching frequency, reducing the inductor ' s footprint. ? monotonic start-up into pre-biased outputs ? adjustable slow start/power sequencing the output voltage startup ramp is controlled by the ss/tr pin which allows operation as either a stand ? power good output monitor for undervoltage and alone power supply or in tracking situations. power overvoltage sequencing is also possible by correctly configuring ? adjustable input undervoltage lockout the enable and the open drain power good pins. ? software tools available cycle by cycle current limiting on the high-side fet ? for swift ? documentation visit protects the device in overload situations and is http://www.ti.com/swift enhanced by a low-side sourcing current limit which prevents current runaway. there is also a low-side 2 applications sinking current limit which turns off the low-side mosfet to prevent excessive reverse current. ? digital tv power supplies hiccup protection will be triggered if the overcurrent ? set top boxes condition has persisted for longer than the preset ? blu-ray dvds time. thermal hiccup protection disables the device when the die temperature exceeds the thermal ? home terminals shutdown temperature and enables the part again ? high performance point of load regulation after the built-in thermal shutdown hiccup time. device information (1) part number package body size (nom) tps54821 vqfn (14) 3.50 mm x 3.50 mm (1) for all available packages, see the orderable addendum at the end of the datasheet. simplified schematic efficiency, v out = 3.3 v, f sw = 480 khz 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. ph pvin gnd boot vsense comp tps54821 en rt/clk ss/tr exposed thermal pad css rrt r3 c1 cboot co lo r1 r 2 cin c2 vin vin vout pwrgd 0 10 20 30 40 50 60 70 80 90 100 0 1 2 3 4 5 6 7 8 output current (a) efficiency (%) v in = 8 v v in = 12 v v in = 17 v g001 productfolder sample &buy technical documents tools & software support &community
tps54821 slvsb14a ? october 2011 ? revised november 2014 www.ti.com table of contents 7.3 feature description ................................................. 11 1 features .................................................................. 1 7.4 device functional modes ........................................ 12 2 applications ........................................................... 1 8 application and implementation ........................ 21 3 description ............................................................. 1 8.1 application information ............................................ 21 4 revision history ..................................................... 2 8.2 typical application .................................................. 21 5 pin configuration and functions ......................... 3 9 power supply recommendations ...................... 29 6 specifications ......................................................... 4 10 layout ................................................................... 30 6.1 absolute maximum ratings ...................................... 4 10.1 pcb layout guidelines ......................................... 30 6.2 handling ratings ....................................................... 4 10.2 layout example .................................................... 31 6.3 recommended operating conditions ....................... 4 11 device and documentation support ................. 33 6.4 thermal information .................................................. 5 11.1 trademarks ........................................................... 33 6.5 electrical characteristics ........................................... 5 11.2 electrostatic discharge caution ............................ 33 6.6 typical characteristics .............................................. 7 11.3 glossary ................................................................ 33 7 detailed description ............................................ 10 12 mechanical, packaging, and orderable 7.1 overview ................................................................. 10 information ........................................................... 34 7.2 functional block diagram ....................................... 11 4 revision history note: page numbers for previous revisions may differ from page numbers in the current version. changes from original (october 2011) to revision a page ? added handling rating table, feature description section, device functional modes, application and implementation section, power supply recommendations section, layout section, device and documentation ............... 1 ? deleted feature: ? 40 c to 125 c operating junction temperature range ......................................................................... 1 ? added the i/o column to the pin functions table .................................................................................................................. 3 ? added i out = 8a and i out = 6a to the operating junction temperature row of the abs max table, also min = -40 and max =150 ........................................................................................................................................................................ 4 2 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: tps54821
tps54821 www.ti.com slvsb14a ? october 2011 ? revised november 2014 5 pin configuration and functions rhl package 14 pins (top view) pin functions pin description i/o name no. automatically selects between rt mode and clk mode. an external timing resistor adjusts the rt/clk 1 i switching frequency of the device; in clk mode, the device synchronizes to an external clock. gnd 2, 3 - return for control circuitry and low-side power mosfet. pvin 4, 5 i power input. supplies the power switches of the power converter. vin 6 i supplies the control circuitry of the power converter. vsense 7 i inverting input of the gm error amplifier. error amplifier output, and input to the output switch current comparator. connect frequency comp 8 i compensation to this pin. slow-start and tracking. an external capacitor connected to this pin sets the internal voltage reference ss/tr 9 i rise time. the voltage on this pin overrides the internal reference. it can be used for tracking and sequencing. en 10 i enable pin. float to enable. adjust the input undervoltage lockout with two resistors. ph 11, 12 o the switch node. a bootstrap cap is required between boot and ph. the voltage on this cap carries the gate drive boot 13 o voltage for the high-side mosfet. power good fault pin. asserts low if output voltage is low due to thermal shutdown, dropout, over- pwrgd 14 o voltage, en shutdown or during slow start. exposed thermal 15 - thermal pad of the package and signal ground and it must be soldered down for proper operation. pad copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 3 product folder links: tps54821 13 boot12 ph 11 ph 10 en 9 ss/tr gnd 2 gnd 3 pvin 4 pvin 5 vin 6 7 8 1 14 rt/clk pwrgd vsense comp (15) exposed thermal pad
tps54821 slvsb14a ? october 2011 ? revised november 2014 www.ti.com 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit vin ? 0.3 20 pvin ? 0.3 20 en ? 0.3 6 boot ? 0.3 27 input voltage vsense ? 0.3 3 v comp ? 0.3 3 pwrgd ? 0.3 6 ss/tr ? 0.3 3 rt/clk ? 0.3 6 boot-ph 0 7.5 output voltage ph ? 1 20 v ph 10ns transient ? 3 20 vdiff (gnd to exposed thermal pad) ? 0.2 0.2 v rt/clk 100 a source current ph current limit a ph current limit a pvin current limit sink current comp 200 a pwrgd ? 0.1 5 ma i out = 8 a ? 40 125 operating junction temperature c i out = 6 a ? 40 150 (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 handling ratings min max unit t stg storage temperature range ? 65 150 c human body model (hbm), per ansi/esda/jedec js-001, all ? 2 2 kv pins (1) v (esd) electrostatic discharge charged device model (cdm), per jedec specification ? 500 500 v jesd22-c101, all pins (2) (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit input voltage range vin 4.5 17 v power stage input voltage range pvin 1.6 17 v output current t j = ? 40 c to 125 c 0 8 a i out = 6 a ? 40 150 c operating junction temperature, t j i out = 8 a ? 40 125 c 4 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: tps54821
tps54821 www.ti.com slvsb14a ? october 2011 ? revised november 2014 6.4 thermal information tps54821 thermal metric (1) (2) units rhl (14 pins) r ja junction-to-ambient thermal resistance 47.2 r ja junction-to-ambient thermal resistance (3) 32 r jctop junction-to-case (top) thermal resistance 64.8 r jb junction-to-board thermal resistance 14.4 c/w jt junction-to-top characterization parameter 0.5 jb junction-to-board characterization parameter 14.7 r jcbot junction-to-case (bottom) thermal resistance 3.2 (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . (2) power rating at a specific ambient temperature t a should be determined with a junction temperature of 125 c. this is the point where distortion starts to substantially increase. thermal management of the pcb should strive to keep the junction temperature at or below 125 c for best performance and long-term reliability. see power dissipation estimate in application section of this data sheet for more information. (3) test board conditions: ( a) 2.5 inches 2.5 inches, 4 layers, thickness: 0.062 inch ( b) 2 oz. copper traces located on the top of the pcb ( c) 2 oz. copper ground planes on the 2 internal layers and bottom layer ( d) 4 0.010 inch thermal vias located under the device package 6.5 electrical characteristics t j = ? 40 c to 125 c, vin = 4.5v to 17v, pvin = 1.6v to 17v (unless otherwise noted) parameter test conditions min typ max unit supply voltage (vin and pvin pins) pvin operating input voltage 1.6 17 v vin operating input voltage 4.5 17 v vin internal uvlo threshold vin rising 4.0 4.5 v vin internal uvlo hysteresis 150 mv vin shutdown supply current en = 0 v 2 5 a vin operating ? non switching supply current vsense = 610 mv 600 800 a enable and uvlo (en pin) enable threshold rising 1.21 1.26 v enable threshold falling 1.10 1.17 input current en = 1.1 v 1.15 a hysteresis current en = 1.3 v 3.3 a voltage reference voltage reference 0 a i out 8a 0.594 0.6 0.606 v mosfet high-side switch resistance boot-ph = 3 v 32 60 m ? high-side switch resistance (1) boot-ph = 6 v 26 40 m ? low-side switch resistance (1) vin = 12 v 19 30 m ? error amplifier error amplifier transconductance (gm) ? 2 a < i comp < 2 a, v (comp) = 1 v 1300 mhos error amplifier dc gain vsense = 0.6 v 1000 4000 v/v error amplifier source/sink v (comp) = 1 v, 100 mv input overdrive 110 a start switching threshold 0.25 v comp to iswitch gm 21 a/v (1) measured at pins copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 5 product folder links: tps54821
tps54821 slvsb14a ? october 2011 ? revised november 2014 www.ti.com electrical characteristics (continued) t j = ? 40 c to 125 c, vin = 4.5v to 17v, pvin = 1.6v to 17v (unless otherwise noted) parameter test conditions min typ max unit current limit high-side switch current limit threshold 10.5 14.5 17 a low-side switch sourcing current limit 9.5 11.5 15 a low-side switch sinking current limit 2 3 4 a hiccup wait time 512 cycles hiccup time before re-start 16384 cycles thermal shutdown thermal shutdown 160 175 c thermal shutdown hysteresis 10 c thermal shutdown hiccup time 16384 cycles timing resistor and external clock (rt/clk pin) minimum switching frequency rrt = 240 k ? (1%) 160 200 240 khz switching frequency rrt = 100 k ? (1%) 400 480 560 khz maximum switching frequency rrt = 29 k ? (1%) 1440 1600 1760 khz minimum pulse width 20 ns rt/clk high threshold 2 v rt/clk low threshold 0.78 v rt/clk falling edge to ph rising edge delay measure at 500 khz with rt resistor in series 66 ns switching frequency range (rt mode set point and 200 1600 khz pll mode) ph (ph pin) measured at 90% to 90% of vin, 25 c, i ph = minimum on time 94 145 ns 2a minimum off time boot-ph 3 v 0 ns boot (boot pin) boot-ph uvlo 2.1 3 v slow start and tracking (ss/tr pin) ss charge current 2.3 a ss/tr to vsense matching v (ss/tr) = 0.4 v 20 60 mv power good (pwrgd pin) vsense threshold vsense falling (fault) 92 % vref vsense rising (good) 94 % vref vsense rising (fault) 106 % vref vsense falling (good) 104 % vref output high leakage vsense = vref, v (pwrgd) = 5.5 v 30 100 na output low i (pwrgd) = 2 ma 0.3 v minimum vin for valid output v (pwrgd) < 0.5v at 100 a 0.6 1 v minimum ss/tr voltage for pwrgd 1.4 v 6 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: tps54821
tps54821 www.ti.com slvsb14a ? october 2011 ? revised november 2014 6.6 typical characteristics figure 1. high-side mosfet on resistance figure 2. low-side mosfet on resistance vs junction temperature vs junction temperature figure 3. voltage reference vs junction temperature figure 4. oscillator frequency vs junction temperature figure 6. en pin hysteresis current figure 5. en pin uvlo threshold vs junction temperature vs junction temperature copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 7 product folder links: tps54821 1.2 1.205 1.21 1.215 1.22 en - uvlo threshold - v vin = 12 v -50 -25 0 25 50 75 100 125 t - junction temperature - c j 3.3 3.35 3.4 3.45 3.5 hysterisis current - a m -50 -25 0 25 50 75 100 125 t - junction temperature - c j vin = 12 v 0.594 0.596 0.598 0.6 0.602 0.604 0.606 v - voltage reference - v ref -50 -25 0 25 50 75 100 125 t - junction temperature - c j 465 470 475 480 485 f - oscillator frequency - khz sw -50 -25 0 25 50 75 100 125 t - junction temperature - c j 15 18 21 24 27 30 -50 -25 0 25 50 75 100 125 tj - junction temperature - deg r - on resistance - m ds(on) w vin = 12 v 20 25 30 35 40 -50 -25 0 25 50 75 100 125 r - on resistance - m ds(on) w t - junction temperature - c j vin = 12 v
tps54821 slvsb14a ? october 2011 ? revised november 2014 www.ti.com typical characteristics (continued) figure 7. en pin pullup current threshold figure 8. shutdown quiescent current vs junction temperature vs input voltage figure 10. slow start charge current figure 9. vin non-switching operating quiescent current vs junction temperature vs input voltage figure 11. ss/tr vsense offset vs junction temperature figure 12. pwrgd threshold vs junction temperature 8 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: tps54821 80 90 100 110 120 -50 -25 0 25 50 75 100 125 t - junction temperature - c j i - ss charge current - a ss m vsense rising vsense falling vsense rising vsense falling vin = 12 v 0.01 0.02 0.03 0.04 -50 -25 0 25 50 75 100 125 t - junction temperature - c j v - ss/tr vsense offset - v off 400 500 600 700 800 3 6 9 12 15 18 v - input voltage - v i non-switching quiesent current - a m t = 125c j t = 25c j t = -40c j 2.1 2.2 2.3 2.4 2.5 -50 -25 0 25 50 75 100 125 t - junction temperature - c j i - slow start charge current - a ss m 1.1 1.125 1.15 1.175 1.2 pullup current - a m -50 -25 0 25 50 75 100 125 t - junction temperature - c j 3 6 9 12 15 18 v - input voltage - v i t = 125c j t = 25c j t = -40c j 0 1 2 3 4 shutdown quiesent current - a m en = 0 v
tps54821 www.ti.com slvsb14a ? october 2011 ? revised november 2014 typical characteristics (continued) figure 13. high-side current limit threshold figure 14. minimum controllable on time vs input voltage vs junction temperature figure 15. minimum controllable duty ratio figure 16. booth-ph uvlo threshold vs junction temperature vs junction temperature copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 9 product folder links: tps54821 2 2.1 2.2 -50 -25 0 25 50 75 100 125 t - junction temperature - c j boot-ph uvlo threshold - a m 3 4 5 6 dmin - minimum controllable duty ratio - % -50 -25 0 25 50 75 100 125 t - junction temperature - c j rt = 100 k , vin = 12 v w 11 12 13 14 15 16 17 t = 125c j t = 25c j t = -40c j high-side current limit threshold - a 3 6 9 12 15 18 v - input voltage - v i 70 80 90 100 110 120 tonmin - minimum controllable on time - ns vin = 12 v -50 -25 0 25 50 75 100 125 t - junction temperature - c j
tps54821 slvsb14a ? october 2011 ? revised november 2014 www.ti.com 7 detailed description 7.1 overview the device is a 17-v, 8-a, synchronous step-down (buck) converter with two integrated n-channel mosfets. to improve performance during line and load transients the device implements a constant frequency, peak current mode control which also simplifies external frequency compensation. the wide switching frequency of 200 khz to 1600 khz allows for efficiency and size optimization when selecting the output filter components. the switching frequency is adjusted using a resistor to ground on the rt/clk pin. the device also has an internal phase lock loop (pll) controlled by the rt/clk pin that can be used to synchronize the switching cycle to the falling edge of an external system clock. the device has been designed for safe monotonic startup into pre-biased loads. the default start up is when vin is typically 4.0v. the en pin has an internal pull-up current source that can be used to adjust the input voltage under voltage lockout (uvlo) with two external resistors. in addition, the en pin can be floating for the device to operate with the internal pull-up current. the total operating current for the device is approximately 600 a when not switching and under no load. when the device is disabled, the supply current is typically less than 2 a. the integrated mosfets allow for high efficiency power supply designs with continuous output currents up to 8 amperes. the mosfets have been sized to optimize efficiency for lower duty cycle applications. the device reduces the external component count by integrating the boot recharge circuit. the bias voltage for the integrated high-side mosfet is supplied by a capacitor between the boot and ph pins. the boot capacitor voltage is monitored by a boot to ph uvlo (boot-ph uvlo) circuit allowing ph pin to be pulled low to recharge the boot capacitor. the device can operate at 100% duty cycle as long as the boot capacitor voltage is higher than the preset boot-ph uvlo threshold which is typically 2.1v. the output voltage can be stepped down to as low as the 0.6v voltage reference (vref). the device has a power good comparator (pwrgd) with hysteresis which monitors the output voltage through the vsense pin. the pwrgd pin is an open drain mosfet which is pulled low when the vsense pin voltage is less than 92% or greater than 106% of the reference voltage vref and asserts high when the vsense pin voltage is 94% to 104% of the vref. the ss/tr (slow start/tracking) pin is used to minimize inrush currents or provide power supply sequencing during power up. a small value capacitor or resistor divider should be coupled to the pin for slow start or critical power supply sequencing requirements. the device is protected from output overvoltage, overload and thermal fault conditions. the device minimizes excessive output overvoltage transients by taking advantage of the overvoltage circuit power good comparator. when the overvoltage comparator is activated, the high-side mosfet is turned off and prevented from turning on until the vsense pin voltage is lower than 104% of the vref. the device implements both high-side mosfet overload protection and bidirectional low-side mosfet overload protections which help control the inductor current and avoid current runaway. the device also shuts down if the junction temperature is higher than thermal shutdown trip point. the device is restarted under control of the slow start circuit automatically after the built-in thermal shutdown hiccup time. 10 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: tps54821
tps54821 www.ti.com slvsb14a ? october 2011 ? revised november 2014 7.2 functional block diagram 7.3 feature description 7.3.1 fixed frequency pwm control the device uses a adjustable fixed frequency, peak current mode control. the output voltage is compared through external resistors on the vsense pin to an internal voltage reference by an error amplifier which drives the comp pin. an internal oscillator initiates the turn on of the high-side power switch. the error amplifier output is converted into a current reference which compares to the high-side power switch current. when the power switch current reaches current reference generated by the comp voltage level the high-side power switch is turned off and the low-side power switch is turned on. 7.3.2 continuous current mode operation (ccm) as a synchronous buck converter, the device normally works in ccm (continuous conduction mode) under all load conditions. 7.3.3 vin and power vin pins (vin and pvin) the device allows for a variety of applications by using the vin and pvin pins together or separately. the vin pin voltage supplies the internal control circuits of the device. the pvin pin voltage provides the input voltage to the power converter system. copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 11 product folder links: tps54821 error amplifier boot charge uvlo current sense oscillator with pll slope compensation maximum clamp voltage reference overload recovery vsense ss/tr comp rt/clk ph boot vin gnd thermal hiccup en enable comparator shutdown logic shutdown enable threshold logic shutdown pwrgd exposed thermal pad power stage & deadtime control logic ls mosfetcurrent limit ov minimum clamp pulse skip i p i h pvin uv hs mosfet current comparator current sense regulator vin boot uvlo ph gnd pvin hiccup shutdown hiccup shutdown
tps54821 slvsb14a ? october 2011 ? revised november 2014 www.ti.com feature description (continued) if tied together, the input voltage for vin and pvin can range from 4.5 v to 17 v. if using the vin separately from pvin, the vin pin must be between 4.5 v and 17 v, and the pvin pin can range from as low as 1.6 v to 17 v. a voltage divider connected to the en pin can adjust the either input voltage uvlo appropriately. adjusting the input voltage uvlo on the pvin pin helps to provide consistent power up behavior. 7.3.4 voltage reference the voltage reference system produces a precise 1% voltage reference over temperature by scaling the output of a temperature stable bandgap circuit. 7.3.5 adjusting the output voltage the output voltage is set with a resistor divider from the output (vout) to the vsense pin. it is recommended to use 1% tolerance or better divider resistors. referring to the application schematic of figure 29 , start with a 10 k for r6 and use equation 1 to calculate r5. to improve efficiency at light loads consider using larger value resistors. if the values are too high the regulator is more susceptible to noise and voltage errors from the vsense input current are noticeable. (1) where vref = 0.6v the minimum output voltage and maximum output voltage can be limited by the minimum on time of the high- side mosfet and bootstrap voltage (boot-ph voltage) respectively. more discussions are located in minimum output voltage and bootstrap voltage (boot) and low dropout operation . 7.3.6 safe start-up into pre-biased outputs the device has been designed to prevent the low-side mosfet from discharging a pre-biased output. during monotonic pre-biased startup, the low-side mosfet is not allowed to sink current until the ss/tr pin voltage is higher than 1.4 v. 7.3.7 error amplifier the device uses a transconductance error amplifier. the error amplifier compares the vsense pin voltage to the lower of the ss/tr pin voltage or the internal 0.6 v voltage reference. the transconductance of the error amplifier is 1300 a/v during normal operation. the frequency compensation network is connected between the comp pin and ground. 7.3.8 slope compensation the device adds a compensating ramp to the switch current signal. this slope compensation prevents sub- harmonic oscillations. the available peak inductor current remains constant over the full duty cycle range. 7.4 device functional modes 7.4.1 enable and adjusting undervoltage lockout the en pin provides electrical on/off control of the device. once the en pin voltage exceeds the threshold voltage, the device starts operation. if the en pin voltage is pulled below the threshold voltage, the regulator stops switching and enters low iq state. the en pin has an internal pull-up current source, allowing the user to float the en pin for enabling the device. if an application requires controlling the en pin, use open drain or open collector output logic to interface with the pin. the device implements internal uvlo circuitry on the vin pin. the device is disabled when the vin pin voltage falls below the internal vin uvlo threshold. the internal vin uvlo threshold has a hysteresis of 150mv. if an application requires either a higher uvlo threshold on the vin pin or a secondary uvlo on the pvin, in split rail applications, then the en pin can be configured as shown in figure 17 , figure 18 and figure 19 . when using the external uvlo function it is recommended to set the hysteresis to be greater than 500mv. 12 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: tps54821 - = vo vref r5 r6 vref
tps54821 www.ti.com slvsb14a ? october 2011 ? revised november 2014 device functional modes (continued) the en pin has a small pull-up current ip which sets the default state of the pin to enable when no external components are connected. the pull-up current is also used to control the voltage hysteresis for the uvlo function since it increases by i h once the en pin crosses the enable threshold. the uvlo thresholds can be calculated using equation 2 and equation 3 . figure 17. adjustable vin undervoltage lock out figure 18. adjustable pvin undervoltage lock out, vin 4.5v figure 19. adjustable vin and pvin undervoltage lock out (2) (3) where i h = 3.3 a, i p = 1.15 a, v enrising = 1.21 v, v enfalling = 1.17 v copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 13 product folder links: tps54821 ( ) - + + enfalling stop enfalling p h r1 v r2 = v v r1 i i 1 ? ? - ? ? ? ? - + ? ? enfalling start stop enrising enfalling p h enrising v v v v r1 = v i i v en ip i h vin tps54821 r 1 r 2 en ip i h pvin tps54821 r 1 r 2
tps54821 slvsb14a ? october 2011 ? revised november 2014 www.ti.com device functional modes (continued) 7.4.2 adjustable switching frequency and synchronization (rt/clk) the rt/clk pin can be used to set the switching frequency of the device in two modes. in rt mode, a resistor (rt resistor) is connected between the rt/clk pin and gnd. the switching frequency of the device is adjustable from 200 khz to 1600 khz by placing a maximum of 240 k and minimum of 29 k ? respectively. in clk mode, an external clock is connected directly to the rt/clk pin. the device is synchronized to the external clock frequency with pll. the clk mode overrides the rt mode. the device is able to detect the proper mode automatically and switch from the rt mode to clk mode. 7.4.3 adjustable switching frequency (rt mode) to determine the rt resistance for a given switching frequency, use equation 4 or the curve in figure 20 . to reduce the solution size one would set the switching frequency as high as possible, but tradeoffs of the supply efficiency and minimum controllable on time should be considered. (4) figure 20. rt set resistor vs switching frequency 7.4.4 synchronization (clk mode) an internal phase locked loop (pll) has been implemented to allow synchronization between 200khz and 1600khz, and to easily switch from rt mode to clk mode. to implement the synchronization feature, connect a square wave clock signal to the rt/clk pin with a duty cycle between 20% to 80%. the clock signal amplitude must transition lower than 0.78v and higher than 2.0v. the start of the switching cycle is synchronized to the falling edge of rt/clk pin. in applications where both rt mode and clk mode are needed, the device can be configured as shown in figure 21 . before the external clock is present, the device works in rt mode and the switching frequency is set by rt resistor. when the external clock is present, the clk mode overrides the rt mode. the first time the sync pin is pulled above the rt/clk high threshold (2 v), the device switches from the rt mode to the clk mode and the rt/clk pin becomes high impedance as the pll starts to lock onto the frequency of the external clock. it is not recommended to switch from the clk mode back to the rt mode because the internal switching frequency drops to 100khz first before returning to the switching frequency set by rt resistor. 14 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: tps54821 fsw ? oscillator frequency ? khz 0 50 100 150 200 250 200 400 600 800 1000 1200 1400 1600 r t ? resistance ? k w ( ) 0.997 2 - w - rrt(k ) = 48000 fsw khz
tps54821 www.ti.com slvsb14a ? october 2011 ? revised november 2014 device functional modes (continued) figure 21. works with both rt mode and clk mode 7.4.5 slow start (ss/tr) the device uses the lower voltage of the internal voltage reference or the ss/tr pin voltage as the reference voltage and regulates the output accordingly. a capacitor on the ss/tr pin to ground implements a slow start time. the device has an internal pull-up current source of 2.3 a that charges the external slow start capacitor. the calculations for the slow start time (tss, 10% to 90%) and slow start capacitor (css) are shown in equation 5 . the voltage reference (vref) is 0.6 v and the slow start charge current (iss) is 2.3 a. (5) when the input uvlo is triggered, the en pin is pulled below 1.21v, or a thermal shutdown event occurs the device stops switching and enters low current operation. at the subsequent power up, when the shutdown condition is removed, the device does not start switching until it has discharged its ss/tr pin to ground ensuring proper soft start behavior. 7.4.6 power good (pwrgd) the pwrgd pin is an open drain output. once the vsense pin is between 94% and 104% of the internal voltage reference the pwrgd pin pull-down is de-asserted and the pin floats. it is recommended to use a pull- up resistor between the values of 10 k ? and 100 k ? to a voltage source that is 5.5 v or less. the pwrgd is in a defined state once the vin input voltage is greater than 1v but with reduced current sinking capability. the pwrgd achieves full current sinking capability once the vin input voltage is above 4.5 v. the pwrgd pin is pulled low when vsense is lower than 92% or greater than 106% of the nominal internal reference voltage. also, the pwrgd is pulled low, if the input uvlo or thermal shutdown are asserted, the en pin is pulled low or the ss/tr pin is below 1.4 v. 7.4.7 bootstrap voltage (boot) and low dropout operation the device has an integrated boot regulator, and requires a small ceramic capacitor between the boot and ph pins to provide the gate drive voltage for the high-side mosfet. the boot capacitor is charged when the boot pin voltage is less than vin and boot-ph voltage is below regulation. the value of this ceramic capacitor should be 0.1 f. a ceramic capacitor with an x7r or x5r grade dielectric with a voltage rating of 10 v or higher is recommended because of the stable characteristics over temperature and voltage. to improve drop out, the device is designed to operate at 100% duty cycle as long as the boot to ph pin voltage is greater than the boot-ph uvlo threshold which is typically 2.1 v. when the voltage between boot and ph drops below the boot-ph uvlo threshold the high-side mosfet is turned off and the low-side mosfet is turned on allowing the boot capacitor to be recharged. in applications with split input voltage rails 100% duty cycle operation can be achieved as long as (vin ? pvin) > 4 v. 7.4.8 sequencing (ss/tr) many of the common power supply sequencing methods can be implemented using the ss/tr, en and pwrgd pins. copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 15 product folder links: tps54821 css(nf) vref(v) tss(ms) = iss( a) m rt/clk tps54821 rrt rt/clk mode select
tps54821 slvsb14a ? october 2011 ? revised november 2014 www.ti.com device functional modes (continued) the sequential method is illustrated in figure 22 using two tps54821 devices. the power good of the first device is coupled to the en pin of the second device which enables the second power supply once the primary supply reaches regulation. figure 22. sequential start up sequence figure 23 shows the method implementing ratio-metric sequencing by connecting the ss/tr pins of two devices together. the regulator outputs ramp up and reach regulation at the same time. when calculating the slow start time the pull-up current source must be doubled in equation 5 . figure 23. ratio-metric start up sequence ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network of r1 and r2 shown in figure 24 to the output of the power supply that needs to be tracked or another voltage reference source. using equation 6 and equation 7 , the tracking resistors can be calculated to initiate the vout2 slightly before, after or at the same time as vout1. equation 8 is the voltage difference between vout1 and vout2. to design a ratio-metric start up in which the vout2 voltage is slightly greater than the vout1 voltage when vout2 reaches regulation, use a negative number in equation 6 and equation 7 for deltav. equation 8 results in a positive number for applications where the vout2 is slightly lower than vout1 when vout2 regulation is achieved. . the deltav variable is zero volt for simultaneous sequencing. to minimize the effect of the inherent ss/tr to vsense offset (vssoffset, 29mv) in the slow start circuit and the offset created by the pull-up current source (iss, 2.3 a) and tracking resistors, the vssoffset and iss are included as variables in the equations. to ensure proper operation of the device, the calculated r1 value from equation 6 must be greater than the value calculated in equation 9 . (6) 16 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: tps54821 d vout2 + v vssoffset r1 = vref iss ss/tr tps54821 en pwrgd ss/tr en pwrgd tps54821 ss/tr en pwrgd ss/tr enpwrgd tps54821 tps54821
tps54821 www.ti.com slvsb14a ? october 2011 ? revised november 2014 device functional modes (continued) (7) (8) (9) figure 24. ratio-metric and simultaneous startup sequence 7.4.9 output overvoltage protection (ovp) the device incorporates an output overvoltage protection (ovp) circuit to minimize output voltage overshoot. for example, when the power supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. if the vsense pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier demands maximum output current. once the condition is removed, the regulator output rises and the error amplifier output transitions to the steady state voltage. in some applications with small output capacitance, the power supply output voltage can respond faster than the error amplifier. this leads to the possibility of an output overshoot. the ovp feature minimizes the overshoot by comparing the vsense pin voltage to the ovp threshold. if the vsense pin voltage is greater than the ovp threshold the high-side mosfet is turned off preventing current from flowing to the output and minimizing output overshoot. when the vsense voltage drops lower than the ovp threshold, the high-side mosfet is allowed to turn on at the next clock cycle. 7.4.10 overcurrent protection the device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side mosfet and the low-side mosfet. high-side mosfet overcurrent protection the device implements current mode control which uses the comp pin voltage to control the turn off of the high- side mosfet and the turn on of the low-side mosfet on a cycle by cycle basis. each cycle the switch current and the current reference generated by the comp pin voltage are compared, when the peak switch current intersects the current reference the high-side switch is turned off. low-side mosfet overcurrent protection copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 17 product folder links: tps54821 ss/tr tps54821 en pwrgd ss/tr tps54821 en pwrgd vout1 vout 2 r1 r2 r3 r4 > - d r1 2800 vout1 180 v v = vout1 vout2 d - d - vref r1 r2 = vout2 + v vref
tps54821 slvsb14a ? october 2011 ? revised november 2014 www.ti.com device functional modes (continued) while the low-side mosfet is turned on its conduction current is monitored by the internal circuitry. during normal operation the low-side mosfet sources current to the load. at the end of every clock cycle, the low-side mosfet sourcing current is compared to the internally set low-side sourcing current limit. if the low-side sourcing current is exceeded the high-side mosfet is not turned on and the low-side mosfet stays on for the next cycle. the high-side mosfet is turned on again when the low-side current is below the low-side sourcing current limit at the start of a cycle. the low-side mosfet may also sink current from the load. if the low-side sinking current limit is exceeded the low-side mosfet is turned off immediately for the rest of that clock cycle. in this scenario both mosfets are off until the start of the next cycle. furthermore, if an output overload condition (as measured by the comp pin voltage) has lasted for more than the hiccup wait time which is programmed for 512 switching cycles, the device will shut down itself and restart after the hiccup time of 16384 cycles. the hiccup mode helps to reduce the device power dissipation under severe overcurrent conditions. 7.4.11 thermal shutdown the internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds 175 c typically. once the junction temperature drops below 165 c typically, the internal thermal hiccup timer will start to count. the device reinitiates the power up sequence after the built-in thermal shutdown hiccup time (16384 cycles) is over. 7.4.12 small signal model for loop response figure 25 shows an equivalent model for the device control loop which can be modeled in a circuit simulation program to check frequency response and transient responses. the error amplifier is a transconductance amplifier with a gm of 1300 a/v. the error amplifier can be modeled using an ideal voltage controlled current source. the resistor roea (3.07 m ? ) and capacitor coea (20.7 pf) model the open loop gain and frequency response of the error amplifier. the 1-mv ac voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. plotting a/c and c/b show the small signal responses of the power stage and frequency compensation respectively. plotting a/b shows the small signal response of the overall loop. the dynamic loop response can be checked by replacing the r l with a current source with the appropriate load step amplitude and step rate in a time domain analysis. figure 25. small signal model for loop response 7.4.13 simple small signal model for peak current mode control figure 26 is a simple small signal model that can be used to understand how to design the frequency compensation. the device power stage can be approximated to a voltage controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. the control to output transfer function is shown in equation 10 and consists of a dc gain, one dominant pole and one esr zero. the quotient of the change in switch current and the change in comp pin voltage (node c in figure 25 ) is the power stage transconductance (gm ps ) which is 21 a/v for the device. the dc gain of the power stage is the product of gm ps 18 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: tps54821 vsense comp vout r1 r3 c1 c2 r2 coea roea gm 1300 m a/v 0.6 v power stage ph r esr c o r l b a c 21 a/v
tps54821 www.ti.com slvsb14a ? october 2011 ? revised november 2014 device functional modes (continued) and the load resistance, r l , as shown in equation 11 with resistive loads. as the load current increases, the dc gain decreases. this variation with load may seem problematic at first glance, but fortunately the dominant pole moves with load current (see equation 12 ). the combined effect is highlighted by the dashed line in figure 27 . as the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-db crossover frequency the same for the varying load conditions which makes it easier to design the frequency compensation. figure 26. simplified small signal model for peak current mode control figure 27. simplified frequency response for peak current mode control (10) (11) (12) (13) where gm ea is the gm amplifier gain ( 1300 a/v) gm ps is the power stage gain (21a/v). r l is the load resistance c o is the output capacitance. r esr is the equivalent series resistance of the output capacitor. copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 19 product folder links: tps54821 o esr 1 z = c r 2 | p o l 1 p = c r 2 | p ps l adc = gm r s 1+ 2 z vout = adc vc s 1+ 2 p ? ? ? | ? ? ? ? | ? pp vout r esr c o r l vc gm ps fp fz adc vout r esr c o r l vc gm ps
tps54821 slvsb14a ? october 2011 ? revised november 2014 www.ti.com device functional modes (continued) 7.4.14 small signal model for frequency compensation the device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used type ii compensation circuits and a type iii frequency compensation circuit, as shown in figure 28 . in type 2a, one additional high frequency pole, c6, is added to attenuate high frequency noise. in type iii, one additional capacitor, c11, is added to provide a phase boost at the crossover frequency. see designing type iii compensation for current mode step-down converters ( slva352 ) for a complete explanation of type iii compensation. the design guidelines below are provided for advanced users who prefer to compensate using the general method. the below equations only apply to designs whose esr zero is above the bandwidth of the control loop. this is usually true with ceramic output capacitors. see the application information section for a step-by-step design procedure using higher esr output capacitors with lower esr zero frequencies. figure 28. types of frequency compensation the general design guidelines for device loop compensation are as follows: 1. determine the crossover frequency, fc. a good starting point is 1/10 th of the switching frequency, fsw. 2. r4 can be determined by: (14) where: gm ea is the gm amplifier gain (1300 a/v) gm ps is the power stage gain (21a/v) vref is the reference voltage (0.6v) 3. place a compensation zero at the dominant pole: c4 can be determined by: (15) 4. c6 is optional. it can be used to cancel the zero from the esr (equivalent series resistance) of the output capacitor co. (16) 5. type iii compensation can be implemented with the addition of one capacitor, c11. this allows for slightly higher loop bandwidths and higher phase margins. if used, c11 is calculated from equation 17 . (17) 20 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: tps54821 ( ) 1 c11 2 r8 fc = p esr r co c6 = r4 l r co c4 = r4 o l 1 p = c r 2 ? ? | ? ? p ea ps 2 c vout co r4 = gm vref gm | p vref vout r8 r4 c4 c6 r9 coea roea gm ea comp vsense type 2a type 2b r4 c4 c11 type 3
tps54821 www.ti.com slvsb14a ? october 2011 ? revised november 2014 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the tps54821 is a highly-integrated, synchronous step-down dc-dc converter. the device is used to convert a higher dc input voltage to a lower dc output voltage with a minimum output current of 8 a. 8.2 typical application figure 29. typical application circuit 8.2.1 design parameters this example details the design of a high frequency switching regulator design using ceramic output capacitors. a few parameters must be known in order to start the design process. these parameters are typically determined at the system level. for this example, use the parameters shown in table 1 . table 1. design parameters parameter value output voltage 3.3 v output current 8 a transient response 4 a load step vout = 7 % input voltage 12 v nominal, 8 v to 17 v output voltage ripple 33 mv p-p start input voltage (rising vin) 6.528 v stop input voltage (falling vin) 6.193 v switching frequency 480 khz copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 21 product folder links: tps54821 vin = 8 - 17 v vout = 3.3 v, 8 a r7 10.0k c7 47uf c3 0.1uf r6 0 r8 2.21k r54.64k c43900pf c539pf c110uf r135.7k r28.06k r3 100k 1 rt/clk 2 gnd 3 gnd 4 pvin 5 pvin 6 vin 7 v_sns 8 comp 9 ss/tr 10 en 11 ph 12 ph 13 boot 14 pwrgd 15 pwpd u1 tps54821rhl c24.7uf c60.022uf c9 470pf l1 3.3 uh c8 47uf r4 100k en v_sns v_sns en pull up voltage pwrgd vin vout
tps54821 slvsb14a ? october 2011 ? revised november 2014 www.ti.com 8.2.2 design guide ? step-by-step design procedure 8.2.2.1 typical application schematic the application schematic of figure 29 was developed to meet the requirements above. this circuit is available as the tps54821evm-049 evaluation module. the design procedure is given in this section. for more information about type ii and type iii frequency compensation circuits, see designing type iii compensation for current mode step-down converters ( slva352 ) and design calculator ( slvc219 ). 8.2.2.2 operating frequency the first step is to decide on a switching frequency for the regulator. there is a trade off between higher and lower switching frequencies. higher switching frequencies may produce smaller a solution size using lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. however, the higher switching frequency causes extra switching losses, which hurt the converter ? s efficiency and thermal performance. in this design, a moderate switching frequency of 480 khz is selected to achieve both a small solution size and a high efficiency operation. 8.2.2.3 output inductor selection to calculate the value of the output inductor, use equation 18 . kind is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. the inductor ripple current is filtered by the output capacitor. therefore, choosing high inductor ripple currents impact the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. in general, the inductor ripple value is at the discretion of the designer; however, kind is normally from 0.1 to 0.3 for the majority of applications. (18) for this design example, use kind = 0.3 and the minimum inductor value is calculated to be 2.31 h. for this design, a larger standard value was chosen: 3.3 h. for the output filter inductor, it is important that the rms current and saturation current ratings not be exceeded. the rms and peak inductor current can be found from equation 20 and equation 21 . (19) (20) (21) for this design, the rms inductor current is 8.015 a and the peak inductor current is 8.839 a. the chosen inductor is a vishay ihlp4040dzer3r3m1series 3.3 h. it has a saturation current rating of 18.6 a (-20% inductance) and a rms current rating of 10 a (40 c temperature rise). the current flowing through the inductor is the inductor ripple current plus the output current. during power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. in transient conditions, the inductor current can increase up to the switch current limit of the device. for this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current. 8.2.2.4 output capacitor selection there are three primary considerations for selecting the value of the output capacitor. the output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. the output capacitance needs to be selected based on the more stringent of these three criteria 22 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: tps54821 2 = + iripple ilpeak iout ( ) 2 2 1 12 f ? ? - = + ? ? ? o v vinmax vo ilrms io vinmax l1 sw f - = vinmax vout vout iripple l1 vinmax sw f - = vinm ax vout vout l1 io kind vinm ax sw
tps54821 www.ti.com slvsb14a ? october 2011 ? revised november 2014 the desired response to a large change in the load current is the first criteria. the output capacitor needs to supply the load with current when the regulator can not. this situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. the regulator is also temporarily not able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as a transition from no load to full load. the regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. the output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. the output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage. equation 22 shows the minimum output capacitance necessary to accomplish this. (22) where iout is the change in output current, fsw is the regulators switching frequency and vout is the allowable change in the output voltage. for this example, the transient load response is specified as a 7% change in vout for a load step of 4 a. for this example, iout = 4 a and vout = 0.07 x 3.3 = 0.231 v. using these numbers gives a minimum capacitance of 72.2 f. this value does not take the esr of the output capacitor into account in the output voltage change. for ceramic capacitors, the esr is usually small enough to ignore in this calculation. equation 23 calculates the minimum output capacitance needed to meet the output voltage ripple specification. where fsw is the switching frequency, vripple is the maximum allowable output voltage ripple, and iripple is the inductor ripple current. in this case, the maximum output voltage ripple is 33mv. under this requirement, equation 23 yields 14.6 f. (23) equation 24 calculates the maximum esr an output capacitor can have to meet the output voltage ripple specification. equation 24 indicates the esr should be less than 17.9 m . in this case, the ceramic caps ? esr is much smaller than 17.9 m . (24) additional capacitance de-ratings for aging, temperature and dc bias should be factored in which increases this minimum value. for this example, 2 x 47 f 10 v x5r ceramic capacitor with 3 m of esr are used. capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. an output capacitor that can support the inductor ripple current must be specified. some capacitor data sheets specify the rms (root mean square) value of the maximum ripple current. equation 25 can be used to calculate the rms ripple current the output capacitor needs to support. for this application, equation 25 yields 485ma. (25) 8.2.2.5 input capacitor selection the tps54821 requires a high quality ceramic, type x5r or x7r, input decoupling capacitor of at least 4.7 f of effective capacitance on the pvin input voltage pins and 4.7 f on the vin input voltage pin. in some applications additional bulk capacitance may also be required for the pvin input. the effective capacitance includes any dc bias effects. the voltage rating of the input capacitor must be greater than the maximum input voltage. the capacitor must also have a ripple current rating greater than the maximum input current ripple of the tps54821. the input ripple current can be calculated using equation 26 . (26) copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 23 product folder links: tps54821 ( ) - = vinmin vout vout icirms iout vinmin vinmin ( ) 12 f - = vout vinmax vout icorms vinmax l1 sw < voripple resr iripple 1 1 8 f > co voripple sw iripple 2 f d > d iout co sw vout
tps54821 slvsb14a ? october 2011 ? revised november 2014 www.ti.com the value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the capacitor. the capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. x5r and x7r ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. the output capacitor must also be selected with the dc bias taken into account. the capacitance value of a capacitor decreases as the dc bias across a capacitor increases. for this example design, a ceramic capacitor with at least a 25 v voltage rating is required to support the maximum input voltage. for this example, one 10 f and one 4.7 f 25 v capacitors in parallel have been selected as the vin and pvin inputs are tied together so the tps54821 may operate from a single supply. the input capacitance value determines the input ripple voltage of the regulator. the input voltage ripple can be calculated using equation 27 . using the design example values, ioutmax = 8 a, cin = 14.7 f, fsw=480 khz, yields an input voltage ripple of 417 mv and a rms input ripple current of 3.94 a. (27) 8.2.2.6 slow start capacitor selection the slow start capacitor determines the minimum amount of time it takes for the output voltage to reach its nominal programmed value during power up. this is useful if a load requires a controlled voltage slew rate. this is also used if the output capacitance is very large and would require large amounts of current to quickly charge the capacitor to the output voltage level. the large currents necessary to charge the capacitor may make the tps54821 reach the current limit or excessive current draw from the input power supply may cause the input voltage rail to sag. limiting the output voltage slew rate solves both of these problems. the soft start capacitor value can be calculated using equation 28 . for the example circuit, the soft start time is not too critical since the output capacitor value is 2 x 47 f which does not require much current to charge to 3.3 v. the example circuit has the soft start time set to an arbitrary value of 6 ms which requires a 22nf capacitor. in tps54821, iss is 2.3 a and vref is 0.6v. (28) 8.2.2.7 bootstrap capacitor selection a 0.1 f ceramic capacitor must be connected between the boot to ph pin for proper operation. it is recommended to use a ceramic capacitor with x5r or better grade dielectric. the capacitor should have 10v or higher voltage rating. 8.2.2.8 under voltage lockout set point the under voltage lock out (uvlo) can be adjusted using the external voltage divider network of r3 and r4. r3 is connected between vin and the en pin of the tps54821 and r4 is connected between en and gnd . the uvlo has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. for the example design, the supply should turn on and start switching once the input voltage increases above 6.528v (uvlo start or enable). after the regulator starts switching, it should continue to do so until the input voltage falls below 6.190 v (uvlo stop or disable). equation 2 and equation 3 can be used to calculate the values for the upper and lower resistor values. for the stop voltages specified the nearest standard resistor value for r3 is 35.7 k ? and for r4 is 8.06 k ? . 8.2.2.9 output voltage feedback resistor selection the resistor divider network r7 and r8 is used to set the output voltage. for the example design, 10 k was selected for r7. using equation 29 , r8 is calculated as 2.22 k . the nearest standard 1% resistor is 2.21 k . (29) 8.2.2.9.1 minimum output voltage due to the internal design of the tps54821, there is a minimum output voltage limit for any given input voltage. the output voltage can never be lower than the internal voltage reference of 0.6 v. above 0.6 v, the output voltage may be limited by the minimum controllable on time. the minimum output voltage in this case is given by equation 30 24 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: tps54821 - ref out ref r7 v r8 = v v ( ) ( ) ( ) m = tss ms iss a c6(nf) vref v 0.25 f d = ioutmax vin cin sw
tps54821 www.ti.com slvsb14a ? october 2011 ? revised november 2014 where: voutmin = minimum achievable output voltage ontimemin = minimum controllable on-time (135 nsec maximum) fsmax = maximum switching frequency including tolerance vinmax = maximum input voltage ioutmin = minimum load current rds1min = minimum high side mosfet on resistance (36-32 m ? typical) rds2min = minimum low side mosfet on resistance (19 m ? typical) rl = series resistance of output inductor (30) 8.2.2.10 compensation component selection there are several possible methods to design closed loop compensation for dc/dc converters. for the ideal current mode control, the design equations can be easily simplified. the power stage gain is constant at low frequencies, and rolls off at ? 20 db/decade above the modulator pole frequency. the power stage phase is 0 degrees at low frequencies and starts to fall one decade above the modulator pole frequency reaching a minimum of ? 90 degrees one decade above the modulator pole frequency. the modulator pole is a simple pole shown in equation 31 (31) for the tps54821 most circuits will have relatively high amounts of slope compensation. as more slope compensation is applied, the power stage characteristics will deviate from the ideal approximations. the phase loss of the power stage will now approach -180 degrees, making compensation more difficult. the power stage transfer function can be solved but it is a tedious hand calculation that does not lend itself to simple approximations. it is best to use pspice or tina-ti to accurately model the power stage gain and phase so that a reliable compensation circuit can be designed. that is the technique used in this design procedure. using the pspice model for the tps54821, apply the values calculated previously to the output filter components of l1, c7 and c8. set r load to the appropriate value for the current value to be compensate. for this design, l1 = 3.3 h. c7 and c8 use the derated capacitance value of 37.6 f, and the esr is set to 3 m . the r load resistor is 3.3 v/4 a = 0.82 . now the power stage characteristic can be plotted as shown in figure 30 . figure 30. power stage gain and phase characteristics copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 25 product folder links: tps54821 frequency 100hz 1.0khz 10khz 100khz 1.0mhz phase - degrees -60 -40 -20 -0 20 40 60 -180d -120d -60d 0d 60d 120d 180d gain - db phase - deg phase - deg gain - db -137 deg -8.281 db | p iout m ax p m od = 2 vout cout ( ) ( ) ( ) voutmin ontimemin fsmax vinmax ioutmin rds2min rds1min iou tmin rl rds2min = + - - +
tps54821 slvsb14a ? october 2011 ? revised november 2014 www.ti.com for this design, the intended crossover frequency is 80 khz. from the power stage gain and phase plots, the gain at 80 khz is -8.281 db and the phase is -137 degrees. for 60 degrees of phase margin, additional phase boost from a feed forward capacitor in parallel with the upper resistor of the voltage set point divider will be required. r5 sets the gain of the compensated error amplifier to be equal and opposite the power stage gain at crossover. the required value of r5 can be calculated from equation 32 . (32) to maximize phase gain, the compensator zero is placed one decade below the crossover frequency of 80 khz. the required value for c4 is given by equation 33 . (33) to maximize phase gain the high frequency pole is placed one decade above the crossover frequency of 80 khz. the required value for c5 can be calculated from equation 34 . (34) the feed forward capacitor c9, is used to increase the phase boost at crossover above what is normally available from type ii compensation. it places an additional zero/pole pair located at equation 35 and equation 36 . (35) (36) this zero and pole pair is not independent. once the zero location is chosen, the pole is fixed as well. for optimum performance, the zero and pole should be located symmetrically about the intended crossover frequency. the required value for c9 can calculated from equation 37 . (37) for this design the calculated values for the compensation components are r5 = 4.68 k ,c4 = 4290 pf, c5 = 42.9 pf and c9 = 467 pf. using standard values, the compensation components are r5 = 4.64 k ,c4 = 3900 pf, c5 = 39 pf and c9 = 470 pf. 8.2.2.11 fast transient considerations in applications where fast transient responses are important, type iii frequency compensation can be used instead of the traditional type ii frequency compensation. 26 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: tps54821 p ref co out 1 c9 = v 2 r7 f v p p p 1 f = 2 c9 r7 r8 p z 1 f = 2 c9 r7 p p 1 c5 = 2 r5 f p co 1 c4 = f 2 r5 10 - pwrstg g 20 out ea ref v 10 r5 = gm v
tps54821 www.ti.com slvsb14a ? october 2011 ? revised november 2014 8.2.3 application curves figure 32. startup with vin figure 31. load transient figure 33. startup with en figure 34. startup with pre-bias figure 35. output voltage ripple with full load figure 36. input voltage ripple with full load copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 27 product folder links: tps54821 v = 20 mv/div (ac coupled) out time = 1 s/div ph = 5 v/div v = 500 mv/div (ac coupled) in time = 1 s/div ph = 5 v/div v = 2 v/div out time = 5 ms/div ss/tr = 1 v/div en = 5 v/div pwrgd = 5 v/div v = 1 v/div (1 v pre-bias) out time = 2 ms/div v = 5 v/div in v = 100 mv/div (ac coupled) out i = 2 a/div out time = 100 s/div 2 a to 6 a load step, slew rate = 1 a / sec v = 2 v/div out time = 5 ms/div ss/tr = 1 v/div v = 10 v/div in pwrgd = 5 v/div
tps54821 slvsb14a ? october 2011 ? revised november 2014 www.ti.com figure 37. closed loop response, i out = 4 a figure 38. line regulation figure 40. tracking performance figure 39. load regulation figure 41. maximum ambient temperature vs load figure 42. efficiency vs load current current 28 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: tps54821 0 10 20 30 40 50 60 70 80 90 100 0 1 2 3 4 5 6 7 8 output current (a) efficiency (%) v in = 8 v v in = 12 v v in = 17 v g001 v = 12 v, v = 3.3 v, fsw = 480 khz, room temp, no air flow in out 25 50 75 100 125 150 0 1 2 3 4 5 6 load current - a t - maximum ambient temperature - c a ?1 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 output current (a) output voltage deviation (%) v in = 12 v g003 0.00001 0.0001 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 track in voltage - v output voltage - v 0.00001 0.0001 0.001 0.01 0.1 1 10 vsense voltage - v vout ideal vsense vsense ?0.02 ?0.015 ?0.01 ?0.005 0 0.005 0.01 0.015 0.02 8 9 10 11 12 13 14 15 16 17 input voltage (v) output voltage deviation (%) i out = 4 a g004 100 1000 10000 100000 1000000 ?60 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 ?180 ?150 ?120 ?90 ?60 ?30 0 30 60 90 120 150 180 frequency (hz) gain (db) phase () gainphase g001
tps54821 www.ti.com slvsb14a ? october 2011 ? revised november 2014 figure 43. efficiency vs output current figure 44. tps54821 hiccup mode current limit 9 power supply recommendations the tps54821 is designed to operate from an input voltage supply range between 4.5 v and 17 v. this supply voltage must be well regulated. power supplies must be well bypassed for proper electrical performance. this includes a minimum of one 4.7 f (after de-rating) ceramic capacitor, type x5r or better from pvin to gnd, and from vin to gnd. additional local ceramic bypass capacitance may be required in systems with small input ripple specifications, in addition to bulk capacitance if the tps54821 device is located more than a few inches away from its input power supply. in systems with an auxiliary power rail available, the power stage input, pvin, and the analog power input, vin, may operate from separate input supplies. see figure 45 (layout recommendation) for recommended bypass capacitor placement. copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 29 product folder links: tps54821 v = 2 v/div out i = 10 a/div out time = 20 ms/div ph = 10 v/div 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 output current (a) efficiency (%) v in = 8 v v in = 12 v v in = 17 v g002
tps54821 slvsb14a ? october 2011 ? revised november 2014 www.ti.com 10 layout 10.1 pcb layout guidelines layout is a critical portion of good power supply design. see figure 45 for a pcb layout example. the top layer contains the main power traces for vin, vout, and vphase. also on the top layer are connections for the remaining pins of the tps54821 and a large top side area filled with ground. the top layer ground area should be connected to the internal ground layer(s) using vias at the input bypass capacitor, the output filter capacitor and directly under the tps54821 device to provide a thermal path from the exposed thermal pad land to ground. the gnd pin should be tied directly to the power pad under the ic and the power pad. for operation at full rated load, the top side ground area together with the internal ground plane, must provide adequate heat dissipating area. there are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. to help eliminate these problems, the pvin pin should be bypassed to ground with a low esr ceramic bypass capacitor with x5r or x7r dielectric. care should be taken to minimize the loop area formed by the bypass capacitor connections, the pvin pins, and the ground connections. the vin pin must also be bypassed to ground using a low esr ceramic capacitor with x5r or x7r dielectric. make sure to connect this capacitor to the quite analog ground trace rather than the power ground trace of the pvin bypass capacitor. since the ph connection is the switching node, the output inductor should be located close to the ph pins, and the area of the pcb conductor minimized to prevent excessive capacitive coupling. the output filter capacitor ground should use the same power ground trace as the pvin input bypass capacitor. try to minimize this conductor length while maintaining adequate width. the small signal components should be grounded to the analog ground path as shown. the rt/clk pin is sensitive to noise so the rt resistor should be located as close as possible to the ic and routed with minimal lengths of trace. the additional external components can be placed approximately as shown. it may be possible to obtain acceptable performance with alternate pcb layouts, however this layout has been shown to produce good results and is meant as a guideline. land pattern and stencil information is provided in the data sheet addendum. the dimension and outline information is for the standard rhl (s-pvqfn-n14) package. there may be slight differences between the provided data and actual lead frame used on the tps54821rhl package. 30 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: tps54821
tps54821 www.ti.com slvsb14a ? october 2011 ? revised november 2014 10.2 layout example figure 45. pcb layout copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 31 product folder links: tps54821 rt/clk gnd pvin vin vsense comp ss/tr en ph boot pwrgd gnd pvin ph ph exposed thermal pad area compensation network boot capacitor pvininput bypass capacitor vout topside ground area via to ground plane output inductor output filter capacitor frequency set resistor slow start capacitor analog ground trace vininput bypass capacitor vin pvin uvlo set resistors feedback resistors etch under component 0.010 in. diameter thermal via to ground plane
tps54821 slvsb14a ? october 2011 ? revised november 2014 www.ti.com layout example (continued) figure 46. ultra-small pcb layout using tps54821 (pmp4854-2) 10.2.1 estimated circuit area the estimated printed circuit board area for the components used in the design of figure 29 is 0.58 in 2 (374mm 2 ). this area does not include test points or connectors. 32 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: tps54821
tps54821 www.ti.com slvsb14a ? october 2011 ? revised november 2014 11 device and documentation support 11.1 trademarks swift is a trademark of texas instruments. all other trademarks are the property of their respective owners. 11.2 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.3 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. copyright ? 2011 ? 2014, texas instruments incorporated submit documentation feedback 33 product folder links: tps54821
tps54821 slvsb14a ? october 2011 ? revised november 2014 www.ti.com 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. 34 submit documentation feedback copyright ? 2011 ? 2014, texas instruments incorporated product folder links: tps54821
package option addendum www.ti.com 20-may-2014 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tps54821rhlr active vqfn rhl 14 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 54821 tps54821rhlt active vqfn rhl 14 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 125 54821 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 20-may-2014 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tps54821rhlr vqfn rhl 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 q2 tps54821rhlt vqfn rhl 14 250 180.0 12.4 3.75 3.75 1.15 8.0 12.0 q2 package materials information www.ti.com 20-may-2014 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) tps54821rhlr vqfn rhl 14 3000 367.0 367.0 35.0 tps54821rhlt vqfn rhl 14 250 210.0 185.0 35.0 package materials information www.ti.com 20-may-2014 pack materials-page 2

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